The present invention relates to the field of semiconductor technology. Embodiments of the invention relate to integrated circuit package structures and manufacturing methods.
In FinFET (Fin Field Effect Transistor) devices, the parasitic resistance has a great influence on the resistance of the source region and the drain region. The parasitic resistance can be caused by a variety of reasons. For example, an important contribution to the parasitic resistance comes from the contact resistance between a metal silicide and the source and drain regions. And the contact between metal silicides with the source and drain regions tends to pinch the Fermi level near the middle of the band gap, which leads to a large Schottky barrier height that increases the contact resistance between the metal silicide and the source region and the drain region.
High resistance in the source and drain regions can have adverse effects in device performance, particularly in FinFET devices. Due to the smaller size, the high resistance of the source and drain regions will reduce the performance of FinFET devices more severely.
Therefore, there is an urgent need for improved techniques for reducing the resistance of the source region and the drain region.